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1. general description the 74hc259-q100; 74hct259-q100 are high-speed si-gate cmos devices and are pin compatible with low-power schottky ttl (lsttl ). they are specifie d in compliance with jedec standard no. 7a. the 74hc259-q100; 74hct259-q100 are high-speed 8-bit addressable latches designed for general-purpose storage applications in digital systems. they are multifunctional devices capable of storing sing le-line data in eight addressable latches and providing a 3-to-8 decoder and multiplexer fu nction with active high outputs (q0 to q7). they also incorporate an active low common reset (mr ) for resetting a ll latches as well as an active low enable input (le ). the 74hc259-q100; 74hct259-q100 has four modes of operation: ? addressable latch mode, in this mode data on the data line (d) is written into the addressed latch. the addressed latch follows the data input with all non-addressed latches remaining in their previous states. ? memory mode, in this mode all latches remain in their previous states and are unaffected by the data or address inputs. ? demultiplexing mode (or 3-to-8 decoding), in this mode the addressed output follows the state of the data input (d) with all other outputs in the low state. ? reset mode, in this mode all outputs are low and unaffected by the address inputs (a0 to a2) and data input (d). when operating the 74hc259-q100; 74hct259-q100 as an address latch, changing more than one address bit could impose a tran sient wrong address. therefore, this should only be done while in the memory mode. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? combined demultiplexer and 8-bit latch ? serial-to-parallel capability ? output from each storage bit available ? random (addressable) data entry ? easily expandable ? common reset input 74hc259-q100; 74hct259-q100 8-bit addressable latch rev. 1 ? 30 july 2012 product data sheet
74hc_hct259_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 30 july 2012 2 of 20 nxp semiconductors 74hc259-q100; 74hct259-q100 8-bit addressable latch ? useful as a 3-to-8 active high decoder ? input levels: ? for 74hc259-q100: cmos level ? for 74hct259-q100: ttl level ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? multiple package options 3. ordering information 4. functional diagram table 1. ordering information type number package temperature range name description version 74hc259d-q100 ? 40 ? c to +125 ? c so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 74hct259d-q100 74hc259pw-q100 ? 40 ? c to +125 ? c tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 74hct259pw-q100 74hc259bq-q100 ? 40 ? c to +125 ? c dhvqfn16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 ? 3.5 ? 0.85 mm sot763-1 74HCT259BQ-Q100 fig 1. logic symbol fig 2. iec logic symbol mna573 d a0 a1 a2 mr le q0 q1 q2 q3 q4 q5 q6 q7 14 15 12 11 10 9 7 6 5 4 3 2 1 13 mna572 1 9,10d z9 g8 g10 c10 8r 13 15 14 0 1 2 3 1 2 0 dx 0 7 2 3 4 5 4 6 7 9 10 11 12 5 6 7 g
74hc_hct259_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 30 july 2012 3 of 20 nxp semiconductors 74hc259-q100; 74hct259-q100 8-bit addressable latch 5. pinning information 5.1 pinning fig 3. functional diagram mna571 8 latches 1-of-8 decoder q0 q1 q2 q3 q4 q5 q6 q7 12 11 10 9 7 6 5 4 a0 a1 a2 le mr d 13 15 14 3 2 1 (1) the die substrate is attached to this pad using conductive die attach mate rial. it cannot be used as supply pin or input. fig 4. pin configuration (so16 and tsso p16) fig 5. pin configuration (dhvqfn16) 74hc259-q100 74hct259-q100 a0 v cc a1 mr a2 le q0 d q1 q7 q2 q6 q3 q5 gnd q4 aaa-003386 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 aaa-003387 74hc259-q100 74hct259-q100 q3 q5 q2 q6 q1 q7 q0 d a2 le a1 mr gnd q4 a0 v cc transparent top view gnd (1) 7 10 6 11 5 12 4 13 3 14 2 15 8 9 1 16 terminal 1 index area
74hc_hct259_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 30 july 2012 4 of 20 nxp semiconductors 74hc259-q100; 74hct259-q100 8-bit addressable latch 5.2 pin description 6. functional description [1] h = high voltage level; l = low voltage level; x = don?t care; d = high or low data one set-up time prior to the low-to-high le transition; q = lower case letter indicates the state of the referenced input one set-up time prior to the low-to-high transition. table 2. pin description symbol pin description a0, a1, a2 1, 2, 3 address input q0, q1, q2, q3, q4, q5, q6, q7 4, 5, 6, 7, 9, 10, 11, 12 latch output gnd 8 ground (0 v) d 13 data input le 14 latch enable input (active low) mr 15 conditional reset input (active low) v cc 16 supply voltage table 3. function table [1] operating mode input output mr le d a0 a1 a2 q0 q1 q2 q3 q4 q5 q6 q7 reset (clear) lhxxxxllllllll demultiplexer (active high 8-channel) decoder (when d = h) lldlllq=dlllllll lldhlllq=dllllll lldlhlllq=dlllll lldhhllllq=dllll lldllhllllq=dlll lldhlhlllllq=dll lldlhhllllllq=dl lldhhhlllllllq=d memory (no action) h h x x x x q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 addressable latch h l d l l l q = d q 1 q 2 q 3 q 4 q 5 q 6 q 7 hl d hl l q 0 q=d q 2 q 3 q 4 q 5 q 6 q 7 hl d l hl q 0 q 1 q=d q 3 q 4 q 5 q 6 q 7 hl d hhl q 0 q 1 q 2 q=d q 4 q 5 q 6 q 7 hldllhq 0 q 1 q 2 q 3 q=d q 5 q 6 q 7 hl d hl hq 0 q 1 q 2 q 3 q 4 q=d q 6 q 7 hl d l hhq 0 q 1 q 2 q 3 q 4 q 5 q=d q 7 hl d hhhq 0 q 1 q 2 q 3 q 4 q 5 q 6 q=d
74hc_hct259_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 30 july 2012 5 of 20 nxp semiconductors 74hc259-q100; 74hct259-q100 8-bit addressable latch [1] h = high voltage level; l = low voltage level. 7. limiting values [1] the input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] for so16 package: p tot derates linearly with 8 mw/k above 70 ? c. for tssop16 package: p tot derates linearly with 5.5 mw/k above 60 ? c. for dhvqfn16 package: p tot derates linearly with 4.5 mw/k above 60 ? c. table 4. operating mode select table [1] le mr mode l h addressable latch mode h h memory mode l l demultiplexer mode hl reset mode table 5. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage ? 0.5 +7.0 v i ik input clamping current v i < ? 0.5 v or v i >v cc +0.5 v [1] - ? 20 ma i ok output clamping current v o < ? 0.5 v or v o > v cc + 0.5 v [1] - ? 20 ma i o output current v o = ? 0.5 v to v cc +0.5v - ? 25 ma i cc supply current - +70 ma i gnd ground current ? 70 - ma t stg storage temperature ? 65 +150 ?c p tot total power dissipation [2] - 500 mw
74hc_hct259_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 30 july 2012 6 of 20 nxp semiconductors 74hc259-q100; 74hct259-q100 8-bit addressable latch 8. recommended operating conditions 9. static characteristics table 6. recommended operating conditions voltages are referenced to gnd (ground = 0 v) symbol parameter conditions 74hc259-q100 74hct259-q100 unit min typ max min typ max v cc supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 v v i input voltage 0 - v cc 0- v cc v v o output voltage 0 - v cc 0- v cc v t amb ambient temperature ? 40 - +125 ? 40 - +125 ?c ? t/ ? v input transition rise and fall rate v cc = 2.0 v - - 625 - - - ns/v v cc = 4.5 v - 1.67 139 - 1.67 139 ns/v v cc = 6.0 v--83---ns/v table 7. static characteristics at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ max min max min max 74hc259-q100 v ih high-level input voltage v cc = 2.0 v 1.5 1.2 - 1.5 - 1.5 - v v cc = 4.5 v 3.15 2.4 - 3.15 - 3.15 - v v cc = 6.0 v 4.2 3.2 - 4.2 - 4.2 - v v il low-level input voltage v cc = 2.0 v - 0.8 0.5 - 0.5 - 0.5 v v cc = 4.5 v - 2.1 1.35 - 1.35 - 1.35 v v cc = 6.0 v - 2.8 1.8 - 1.8 - 1.8 v v oh high-level output voltage v i = v ih or v il i o = ? 20 ? a; v cc = 2.0 v 1.9 2.0 - 1.9 - 1.9 - v i o = ? 20 ? a; v cc = 4.5 v 4.4 4.5 - 4.4 - 4.4 - v i o = ? 20 ? a; v cc = 6.0 v 5.9 6.0 - 5.9 - 5.9 - v i o = ? 4.0 ma; v cc = 4.5 v 3.98 4.32 - 3.84 - 3.7 - v i o = ? 5.2 ma; v cc = 6.0 v 5.48 5.81 - 5.34 - 5.2 - v v ol low-level output voltage v i = v ih or v il i o = 20 ? a; v cc = 2.0 v - 0 0.1 - 0.1 - 0.1 v i o = 20 ? a; v cc = 4.5 v - 0 0.1 - 0.1 - 0.1 v i o = 20 ? a; v cc = 6.0 v - 0 0.1 - 0.1 - 0.1 v i o = 4.0 ma; v cc = 4.5 v - 0.15 0.26 - 0.33 - 0.4 v i o = 5.2 ma; v cc = 6.0 v - 0.16 0.26 - 0.33 - 0.4 v i i input leakage current v i = v cc or gnd; v cc =6.0v -- ? 0.1 - ? 1- ? 1 ? a i cc supply current v i = v cc or gnd; i o =0a; v cc =6.0v - - 8.0 - 80 - 160 ? a
74hc_hct259_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 30 july 2012 7 of 20 nxp semiconductors 74hc259-q100; 74hct259-q100 8-bit addressable latch c i input capacitance -3.5- - - - -pf 74hct259-q100 v ih high-level input voltage v cc = 4.5 v to 5.5 v 2.0 1.6 - 2.0 - 2.0 - v v il low-level input voltage v cc = 4.5 v to 5.5 v - 1.2 0.8 - 0.8 - 0.8 v v oh high-level output voltage v i = v ih or v il ; v cc = 4.5 v i o = ? 20 ? a 4.4 4.5 - 4.4 - 4.4 - v i o = ? 4.0 ma 3.98 4.32 - 3.84 - 3.7 - v v ol low-level output voltage v i = v ih or v il ; v cc = 4.5 v i o = 20 ? a; v cc = 4.5 v - 0 0.1 - 0.1 - 0.1 v i o = 5.2 ma; v cc = 6.0 v - 0.15 0.26 - 0.33 - 0.4 v i i input leakage current v i = v cc or gnd; v cc =5.5v -- ? 0.1 - ? 1- ? 1 ? a i cc supply current v i = v cc or gnd; i o =0a; v cc =5.5v - - 8.0 - 80 - 160 ? a ? i cc additional supply current v i =v cc ? 2.1 v; i o =0a; other inputs at v cc or gnd; v cc = 4.5 v to 5.5 v pin an, le - 150 540 - 675 - 735 ? a pin d - 120 432 - 540 - 588 ? a pin mr - 75 270 - 338 - 368 ? a c i input capacitance -3.5- - - - -pf table 7. static characteristics ?continued at recommended operating conditions; volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ max min max min max
74hc_hct259_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 30 july 2012 8 of 20 nxp semiconductors 74hc259-q100; 74hct259-q100 8-bit addressable latch 10. dynamic characteristics table 8. dynamic characteristics voltages are referenced to gnd (ground = 0 v); for test circuit see figure 12 . symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ [1] max min max min max 74hc259-q100 t pd propagation delay d to qn; see figure 6 [2] v cc = 2.0 v - 58 185 - 230 - 280 ns v cc = 4.5 v - 21 37 - 46 - 56 ns v cc = 5.0 v; c l =15pf - 18 - - - - - ns v cc = 6.0 v - 17 31 - 39 - 48 ns an to qn; see figure 7 [2] v cc = 2.0 v - 58 185 - 230 - 280 ns v cc = 4.5 v - 21 37 - 46 - 56 ns v cc = 5.0 v; c l =15pf - 17 - - - - - ns v cc = 6.0 v - 17 31 - 39 - 48 ns le to qn; see figure 8 [2] v cc = 2.0 v - 55 170 - 215 - 255 ns v cc = 4.5 v - 20 34 - 43 - 51 ns v cc = 5.0 v; c l =15pf - 17 - - - - - ns v cc = 6.0 v - 16 29 - 37 - 43 ns t phl high to low propagation delay mr to qn; see figure 9 v cc = 2.0 v - 50 155 - 195 - 235 ns v cc = 4.5 v - 18 31 - 39 - 47 ns v cc = 5.0 v; c l =15pf - 15 - - - - - ns v cc = 6.0 v - 14 26 - 33 - 40 ns t t transition time see figure 8 [3] v cc = 2.0 v - 19 75 - 95 - 119 ns v cc = 4.5 v - 7 15 - 19 - 22 ns v cc = 6.0 v - 6 13 - 16 - 19 ns t w pulse width le high or low; see figure 8 v cc = 2.0 v 70 17 - 90 - 105 - ns v cc = 4.5 v 14 6 - 18 - 21 - ns v cc = 6.0 v 12 5 - 15 - 18 - ns mr low; see figure 9 v cc = 2.0 v 70 17 - 90 - 105 - ns v cc = 4.5 v 14 6 - 18 - 21 - ns v cc = 6.0 v 12 5 - 15 - 18 - ns
74hc_hct259_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 30 july 2012 9 of 20 nxp semiconductors 74hc259-q100; 74hct259-q100 8-bit addressable latch t su set-up time d, an to le ; see figure 10 and figure 11 v cc = 2.0 v 80 19 - 100 - 120 - ns v cc = 4.5 v 16 7 - 20 - 24 - ns v cc = 6.0 v 14 6 - 17 - 20 - ns t h hold time d to le ; see figure 10 and figure 11 v cc = 2.0 v 0 ? 19 - 0 - 0 - ns v cc = 4.5 v 0 ? 6- 0 - 0 -ns v cc = 6.0 v 0 ? 5- 0 - 0 -ns an to le ; see figure 10 and figure 11 v cc = 2.0 v 2 ? 11 - 2 - 2 - ns v cc = 4.5 v 2 ? 4- 2 - 2 -ns v cc = 6.0 v 2 ? 3- 2 - 2 -ns c pd power dissipation capacitance f i = 1 mhz; v i =gndtov cc [4] -19- - - - -pf 74hct259-q100 t pd propagation delay d to qn; see figure 6 [2] v cc = 4.5 v - 23 39 - 49 - 59 ns v cc = 5.0 v; c l =15pf - 20 - - - - - ns an to qn; see figure 7 [2] v cc = 4.5 v - 25 41 51 62 ns v cc = 5.0 v; c l =15pf - 20 - - - - - ns le to qn; see figure 8 [2] v cc = 4.5 v - 22 38 - 48 - 57 ns v cc = 5.0 v; c l =15pf - 20 - - - - - ns t phl high to low propagation delay mr to qn; see figure 9 v cc = 4.5 v - 23 39 - 49 - 59 ns v cc = 5.0 v; c l =15pf - 20 - - - - - ns t t transition time see figure 8 [3] v cc = 4.5 v - 7 15 - 19 - 22 ns t w pulse width le high or low; see figure 8 v cc = 4.5 v 19 11 - 24 - 29 - ns mr low; see figure 9 v cc = 4.5 v 18 10 - 23 - 27 - ns table 8. dynamic characteristics ?continued voltages are referenced to gnd (ground = 0 v); for test circuit see figure 12 . symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ [1] max min max min max
74hc_hct259_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 30 july 2012 10 of 20 nxp semiconductors 74hc259-q100; 74hct259-q100 8-bit addressable latch [1] typical values are measured at nominal supply voltage (v cc = 3.3 v and v cc =5.0v). [2] t pd is the same as t plh and t phl . [3] t t is the same as t thl and t tlh . [4] c pd is used to determine the dynamic power dissipation (p d in ? w). p d =c pd ? v cc 2 ? f i ? n+ ? (c l ? v cc 2 ? f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in v; n = number of inputs switching; ? (c l ? v cc 2 ? f o ) = sum of the outputs. 11. waveforms t su set-up time d, an to le ; see figure 10 and figure 11 v cc = 4.5 v 17 10 - 21 - 26 - ns t h hold time d to le ; see figure 10 and figure 11 v cc = 4.5 v 0 ? 8- 0 - 0 -ns an to le ; see figure 10 and figure 11 v cc = 4.5 v 0 ? 4- 0 - 0 -ns c pd power dissipation capacitance f i = 1 mhz; v i =gndtov cc ? 1.5 v [4] -19- - - - -pf table 8. dynamic characteristics ?continued voltages are referenced to gnd (ground = 0 v); for test circuit see figure 12 . symbol parameter conditions 25 ?c ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ [1] max min max min max measurement points are given in table 9 . v ol and v oh are typical voltage output levels that occur with the output load. fig 6. data input to output propagation delays 001aah123 d input qn output t phl t plh gnd v cc v m v m v oh v ol
74hc_hct259_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 30 july 2012 11 of 20 nxp semiconductors 74hc259-q100; 74hct259-q100 8-bit addressable latch measurement points are given in table 9 . v ol and v oh are typical voltage output levels that occur with the output load. fig 7. address input to output propagation delays 001aah122 an input qn output t phl t plh gnd v cc v m v m v oh v ol measurement points are given in table 9 . v ol and v oh are typical voltage output levels that occur with the output load. fig 8. enable input to output propagation delays and pulse width t phl v cc gnd d input le input qn output t thl t tlh t w v m v y v m v x t plh v cc gnd v oh v ol 001aaj446 measurement points are given in table 9 . v ol and v oh are typical voltage output levels that occur with the output load. fig 9. master reset input to output propagation delays 001aah124 mr input qn output t phl t w v m v oh v cc gnd v ol v m
74hc_hct259_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 30 july 2012 12 of 20 nxp semiconductors 74hc259-q100; 74hct259-q100 8-bit addressable latch measurement points are given in table 9 . the shaded areas indicate when the input is per mitted to change for predictable output performance. v ol and v oh are typical voltage output levels that occur with the output load. fig 10. data input to latch enable input set-up and hold times 001aah125 gnd gnd t h t su t h t su v m v m v m v cc v oh v ol v cc qn output q = d q = d le input d input measurement points are given in table 9 . the shaded areas indicate when the input is per mitted to change for predictable output performance. v ol and v oh are typical voltage output levels that occur with the output load. fig 11. address input to latch enable input set-up and hold times 001aah126 v m address stable v m t h t su v cc gnd v cc gnd le input an input table 9. measurement points type input output v m v m v x v y 74hc259-q100 0.5v cc 0.5v cc 0.1v cc 0.9v cc 74hct259-q100 1.3 v 1.3 v 0.1v cc 0.9v cc
74hc_hct259_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 30 july 2012 13 of 20 nxp semiconductors 74hc259-q100; 74hct259-q100 8-bit addressable latch test data is given in table 10 . definitions test circuit: r t = termination resistance should be equal to output impedance z o of the pulse generator. c l = load capacitance including jig and probe capacitance. r l = load resistance. s1 = test selection switch fig 12. load circuit for measuring switching times v m v m t w t w 10 % 90 % 0 v v i v i negative pulse positive pulse 0 v v m v m 90 % 10 % t f t r t r t f 001aad983 dut v cc v cc v i v o r t r l s1 c l open g table 10. test data type input load s1 position v i t r , t f c l r l t phl , t plh 74hc259-q100 v cc 6ns 15pf, 50 pf 1k ? open 74hct259-q100 3 v 6 ns 15 pf, 50 pf 1 k ? open
74hc_hct259_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 30 july 2012 14 of 20 nxp semiconductors 74hc259-q100; 74hct259-q100 8-bit addressable latch 12. package outline fig 13. package outline sot109-1 (so16) x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot109-1 99-12-27 03-02-19 076e07 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1
74hc_hct259_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 30 july 2012 15 of 20 nxp semiconductors 74hc259-q100; 74hct259-q100 8-bit addressable latch fig 14. package outline sot403-1 (tssop16) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot403-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 18 16 9 a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 a max. 1.1 pin 1 index
74hc_hct259_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 30 july 2012 16 of 20 nxp semiconductors 74hc259-q100; 74hct259-q100 8-bit addressable latch fig 15. package outline sot763-1 (dhvqfn16) terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 3.6 3.4 d h 2.15 1.85 y 1 2.6 2.4 1.15 0.85 e 1 2.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot763-1 mo-241 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot763-1 dhvqfn16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 27 15 10 9 8 1 16 x d e c b a terminal 1 index area ac c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1) 02-10-17 03-01-27
74hc_hct259_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 30 july 2012 17 of 20 nxp semiconductors 74hc259-q100; 74hct259-q100 8-bit addressable latch 13. abbreviations 14. revision history table 11. abbreviations acronym description cdm charged device model cmos complementary metal-oxide semiconductor dut device under test esd electrostatic discharge hbm human body model lsttl low-power schottky transistor-transistor logic mm machine model ttl transistor-transistor logic table 12. revision history document id release date data sheet status change notice supersedes 74hc_hct259_q100 v.1 20120730 product data sheet - -
74hc_hct259_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 30 july 2012 18 of 20 nxp semiconductors 74hc259-q100; 74hct259-q100 8-bit addressable latch 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 15.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use in automotive applications ? this nxp semiconductors product has been qualified for use in automotive applications. unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
74hc_hct259_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 30 july 2012 19 of 20 nxp semiconductors 74hc259-q100; 74hct259-q100 8-bit addressable latch no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any licens e under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors 74hc259-q100; 74hct259-q100 8-bit addressable latch ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 30 july 2012 document identifier: 74hc_hct259_q100 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 functional description . . . . . . . . . . . . . . . . . . . 4 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 recommended operating conditions. . . . . . . . 6 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 6 10 dynamic characteristics . . . . . . . . . . . . . . . . . . 8 11 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 17 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 18 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 15.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 16 contact information. . . . . . . . . . . . . . . . . . . . . 19 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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